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DEMO CLOUD SOFTWARE
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TCDG
VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
Features
High Performance
16 clock cycles for a complete DES encryption or decryption
Simple interface with a start/done handshake
No external logic necessary
Compatibility
Based on the FIPS PUB 44-2 specification
ANSI X3.92, ANSI X3.106
Suitable for triple DES implementations
Suitable for electronic code block (ECB), cipher block coding (CBC), cipher feedback (CFB) and output feedback (OFB) implementations
Description language & Synthesis caracteristics
Available in VHDL and Verilog
Described for both synthesis and simulation
Fully Synchronous design
Low gate count
High clock speed
Test bench provided
Target Technology
FPGA
ASIC
Gate Array
....
Typical application
Data files protection on any media (hard disk, CD-ROM, EEPROM,...)
Access authentification
Smart card applications
Internet & Intranet communication protection
Space telecommunication
Banking applications
Private informations protections
Download
Datasheet
VHDL source code
VHDL test bench source code
Interface
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