TCTF64
VHDL & Verilog Synthesizable model of the Triple DES in Cipher Feedback mode, 64-bit data
Features
High Performance
- 48 clock cycles for a complete Triple DES encryption or decryption
- Simple interface with a start/done handshake
- No external logic necessary
Compatibility
- Based on the FIPS PUB 44-2 specification
- ANSI X3.92, ANSI X9.52
Description language & Synthesis caracteristics
- Available in VHDL and Verilog
- Described for both synthesis and simulation
- Fully Synchronous design
- Low gate count
- High clock speed
- Test bench provided
Target Technology
Typical application
- Data files protection on any media (hard disk, CD-ROM, EEPROM,...)
- Access authentification
- Smart card applications
- Internet & Intranet communication protection
- Space telecommunication
- Banking applications
- Private informations protections
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