TCTF64

VHDL & Verilog Synthesizable model of the Triple DES in Cipher Feedback mode, 64-bit data

High Performance

• 48 clock cycles for a complete Triple DES encryption or decryption
• Simple interface with a start/done handshake
• No external logic necessary

• Based on the FIPS PUB 44-2 specification
• ANSI X3.92, ANSI X9.52

• Available in VHDL and Verilog
• Described for both synthesis and simulation
• Fully Synchronous design
• Low gate count
• High clock speed
• Test bench provided

• FPGA
• ASIC
• Gate Array
• ...

• Data files protection on any media (hard disk, CD-ROM, EEPROM,...)
• Access authentification
• Smart card applications
• Internet & Intranet communication protection
• Space telecommunication
• Banking applications
• Private informations protections

			Datasheet
			VHDL source code
			VHDL test bench source code